His research interests include computer architecture, supercomputing, parallel and pipeline processing, performance modeling, application code assessment and tuning, and intelligent caches. With his graduate students, he developed the reservation table approach to optimum design and cyclic scheduling of pipelines, designed and implemented a n 8 microprocessor SMP system in 1976, and developed a variety of systematic methods for computer performance evaluation. His current research focuses on extending such techniques to evaluate and improve the performance of application codes on parallel, vector, and workstation architectures – - and on intelligent cache design and management.
He has supervised 45 PhD and 38 MS students, was elected Fellow
of the IEEE (1984) for "contributions to the use of pipeline structures
in computer architecture" and Chair of ACM-SIGARCH (l979-l983). He received
the IEEE Computer Society's Harry M. Goode Memorial Award (1992) for "pivotal
seminal contributions to the design, implementation, and performance evaluation
of high performance computer systems" and its Taylor L. Booth Education
Award (1996) "for contributions to the establishment of computer engineering
as an academic discipline and for nurturing many leaders of this field
during their formative years in the profession."