Edward S. Davidson received a BA in mathematics (Harvard University, l96l), an M.S. in communication science (University of Michigan, l962), and a PhD. in EE (University of Illinois, l968).  After working at Honeywell ('62-65), and on the faculties of Stanford University ('68-73), and the University of Illinois ('73-87), he joined The University of Michigan as professor of EECS, served as its chair through 1990, and as chair of computer science and engineering since fall 1997. He managed the hardware design of the Cedar parallel supercomputer at the Center for Supercomputing Research and Development (1984-87) and directed Michigan's Center for Parallel Computing (1994-97).

 His research interests include computer architecture, supercomputing, parallel and pipeline processing, performance modeling, application code assessment and tuning, and intelligent caches. With his graduate students, he developed the reservation table approach to optimum design and cyclic scheduling of pipelines, designed and implemented a n 8 microprocessor SMP system in 1976, and developed a variety of systematic methods for computer performance evaluation. His current research focuses on extending such techniques to evaluate and improve the performance of application codes on parallel, vector, and workstation architectures - and on intelligent  cache design and management.

 He has supervised 45 PhD and 38 MS students, was elected Fellow of the IEEE (1984) for "contributions to the use of pipeline structures in computer architecture" and Chair of ACM-SIGARCH (l979-l983). He received the IEEE Computer Society's Harry M. Goode Memorial Award (1992) for "pivotal seminal contributions to the design, implementation, and performance evaluation of high performance computer systems" and its Taylor L. Booth Education Award (1996) "for contributions to the establishment of computer engineering as an academic discipline and for nurturing many leaders of this field during their formative years in the profession."