April 24-25, 2000
Austin, Texas, USA

Monday, April 24, 2000

8:00am-9:00am Breakfast

9:00am-10:00am  Keynote Address

Introduction/Welcoming Remarks: Dr. Nadeem Malik, General Chair, ISPASS-2000

          Keynote Speech:

The Mission of Performance Analysis: A FUNCTIONAL APPROACH
Prof. Edward S. Davidson
University of Michigan

10:00am-12:00pm  Performance Analysis I

Chair: Peter Magnusson, Virtutech
SPROF/SPROG: Performance Analysis through Synthetic Trace Generation
Lieven Eeckhout, Koen De Bosschere, and Henk Neefs
Universiteit Gent

Extracting Fine Grain profiles of In-Order Executions of  Instruction Level Parallel Programs
Nicola Zingirian Massimo, and Maresca
University of Padova

Accurate Simulation and Evaluation of Code Reordering
David Kaeli and John Kalamatianos
Northeastern University

Quantifying Instruction-Level Parallelism Limits on an EPIC Architecture
Hsien-Hsin Lee, Youfeng Wu, and Gary Tyson
University of Michigan

12:00pm-1:15pm  LUNCH

12:30pm-1:15pm Luncheon Speech
Speaker Introduction: Carol Logan, IBM
Performance Engineered Software and Hardware Systems
Dr. Frederica Darema
Senior Science and Technology Advisor,  NSF/CISE

Parallel Afternoon Sessions

1:15pm-3:15pm Real-Time I (TRACK 1)

Chair: Doug Jensen, MITRE
Performance Evaluation of Real-Time Scheduling On a Multicomputer Architecture
Luis Friedrich, Rafael Cancian, Romulo S. de Oliveira, and Thadeu B. Corso
Universidade Federal de Santa Catarina

Performance Evaluation of Middleware Bridging Technologies
Rod Fatoohi, Vandana Gunwani, Qi Wang, and Charlton Zheng
San Jose State University

A Practitioner Report on the Evaluation of the Performance of the C, C++, & Java Compilers on OS/390
David Cargill and Mohammad Radaideh
IBM Canada Ltd.

DB2 for OS/390 V5 Vs V6 Outer Join Performance
Maryela Weihrauch

1:45pm-3:15pm Performance Analysis II (TRACK 2)

Chair: Dave Kaeli, Northeastern Univ.
Issues in the Design of Store Buffers in Dynamically Scheduled Processors
Ravi Bhargava and Lizy K. John
University of Texas at Austin

Performance Tradeoffs in Sequencer Design on a New G4 PowerPC(TM)
Jeff Rupley II and David C. Holloway
Motorola Somerset Design Center

Trading off Instructions for Locality in Wide Issue Superscalar Processors
Murali Annavarm, Gary S. Tyson, and Edward S. Davidson
University of Michigan

3:15pm-3:30pm Coffee Break

3:30-5:30 Real Time II (TRACK 1)

Chair: Martin Timmerman, DS-Experts
Checking Order-insensitivity using Ternary Simulation in Synchronous Programs
Moez Yeddes Hassane Alla
Laboratoire d'Automatique de Grenoble

Do Generational Schemes Improve the Garbage Collection Efficiency?
Illinois Institute of Technology
Witawas Srisa-an

A Quantitative Simulator for Dynamic Memory Managers
Illinois Institute of Technology
Chia-Tien Dan Lo, Witawas Srisa-an and J. Morris Chang

Real-Time Image on QoS Web
Hong Liu and Hongdu Fang
University of Massachusetts Dartmouth

3:30pm-5:00pm  Workload Characterization I (Track 2)

Chair: Doug Burger, UT Austin
Modeling Load Address Behavior Through Recurrences
Luis M. Ramos, Pablo Ibanez, Victor Vinals, and J. M. Llaberia
Centro Politecnico Superior

Methodology to Optimize the Cost/Performance of Disk Subsystems
Todd Boyd and Renato Recio
IBM Poughkeepsie

Invocation Profile Characterization of Java Applications
Francesco Bellotti, Andrea Barisone, Riccardo Berta, and Allessandro De Gloria
University of Genoa

6:30pm-8:30pm Reception

Tuesday, April 25, 2000

8:00am-9:00am Breakfast

9am-10am  Real Time Tutorial

Speaker Introduction: Nadeem Malik, IBM
Testing Commercial RTOS
by M. Timmerman
Real-Time Consult and Royal Military Academy, Belgium

10:15-12:15 Performance Analysis III

Chair: Pradip Bose, IBM
Invited Paper:  Some Observations based on a Simple Model of MP Scaling
Eric Kronstadt
IBM T. J. Watson Research Center

Performance Scalability in Multiprocessor Systems with Resource Contention
Shikharesh Majumdar
Carleton University

An Efficient Solver for Cache Miss Equations
Antoinio Gonzalez, Nerina Bermudo, Xavier Vera, adn Josep LLosa
Universitat Politecnica de Catalunya

An Analytical Model for Loop Tiling and its Solution
Vivek Sarkar and Nimrod Megdido
IBM T. J. Watson Research Center and IBM Almaden

12:15-1:45  LUNCH

1:45-3:15  Workload Characterization II

Chair: Lizy John, UT Austin
Invited   CommBench---A Telecommunications Benchmark for Network Processors
Tilman Wolf and Mark Franklin
Washington University

Simplified Workload Characterization Using Unified Prediction
Karel Driesen, Josee Colette, Feng Ji, et al.
McGill University

A New Approach in the Analysis and Modeling of Disk Access Patterns
Maria Gomez and Vicente Santonja
Universidad Politecnica de Valencia

3:15-3:30 Coffee Break

3:30-5:30 Web-Enabled Software and Systems

Chair: Craig Chase, UT Austin
Invited Talk:  Mobile Functionality in a Pervasive World
Jerzy Jagiello, et al.
Department of Defence, Australia

A Server Performance Model for Static Web Workloads
Krishna Kant and C.R.M. Sunderam

Design Alternatives for Scalable Web Server Accelerators
Junehwa Song, Eric Levy-Abegnoli, Arun Iyengar, and Daniel Dias
IBM T. J. Watson Research Center

Web Latency Reduction via Client-Side Prefetching
Trevor Mudge, Avinoam N. Eden, and Brian W. Joh
University of Michigan