The 2004 IEEE International Symposium on Performance Analysis of Systems and Software is sponsored by the IEEE Computer Society's Technical Committee on InternetTechnical Committee on Computer Architecture , and Technical Committee on Microprogramming and Microarchitecture .



Day 1

March 10 

 - Keynote I  ( Yale Patt, The University of Texas )

 - Session 1: Benchmarking and Workload Characterization

 - Session 2: Simulation

 - Session 3: Architecture and Performance Evaluation

Day 2

March 11

 - Keynote II   ( Carl Anderson, IBM )

 - Session 4: Memory and Caches

 - Session 5: Java

 - Session 6: Power Estimation and Reduction

 - Panel Discussion: The Future of Simulation: A Field of Dreams?

 - Reception

Day 3

March 12


   - Morning Session

      :Efficient Architectural Design of High Performance Microprocessors

   - Afternoon Session

       :Architectures and Compilers for Multimedia



Day 1 - March 10 (Wednesday)


   8:00 -   9:00     Breakfast

    9:00 - 10:00     Opening and Keynote I   ( Yale Patt, The University of Texas at Austin )                              

Performance analysis can be one of the most important elements in the design cycle of a computer system. It can also be very important after the fact to influence future designs. But only if it is done right. If done wrong, it can be more harmful than if not done at all.


 (Chair: Lizy John, The University of Texas at Austin)


10:00 - 10:20     Break


10:20 - 12:00     Session 1: Benchmarking and Workload Characterization

                             (Chair: Ravi Bhargava, AMD)

Hans Vandierendonck and Koen De Bosschere (Ghent University, Belgium)

Jaidev P. Patwardhan, Alvin R. Lebeck and Daniel J. Sorin (Duke University)

Erik Berg and Erik Hagersten (Uppsala University, Sweden)

 P. Balaji, S. Narravula, K. Vaidyanathan, S. Krishnamoorthy, J. Wu and D. K. Panda (The Ohio State University)

12:00 - 1:30     Lunch


  1:30 - 2:45     Session 2: Simulation

                           (Chair: Brian O'Krafka, Sun Microsystems)

Leonardo R. Bachega, Jose R. Brunheroto, Luiz DeRose, Pedro Mindlin and Jose E. Moreira (IBM Thomas J. Watson Research Center)

Michael Van Biesbrouck, Timothy Sherwood* and Brad Calder (University of California, San Diego, University of California, Santa Barbara*)

Jeremy Lau, Stefan Schoenmackers and Brad Calder (University of California, San Diego)

  2:45 - 3:15     Break

  3:15 - 4:30     Session 3: Architecture and Performance Evaluation

                           (Chair: Erik Altman, IBM)

Gordon B. Bell and Mikko H. Lipasti (University of Wisconsin)

Liem Tran, Nicholas Nelson, Fung Ngai, Steve Dropsho and Michael Huang (University of Rochester)

Ying Zheng, Brian T. Davis and Matthew Jordan (Michigan Technological University)


Day 2 - March 11 (Thursday)


   8:00 -   9:00     Breakfast

    9:00 - 10:00     Keynote II ( Carl Anderson, IBM )

Projections of Information Technology (IT) future will be described. Forecasts of both hardware and software technology trends and ways in which those trends will come together to enable new uses and capabilities for IT. Important trends in key technologies such as raw computing speed, bandwidth, and storage and display capabilities will be shown. New technologies that have the potential of transforming the performance and characteristics of tomorrow's information processing systems and devices are explored.


(Chair: Nadeem Malik, IBM)


 10:00 - 10:20     Break


  10:20 - 12:00     Session 4: Memory and Caches

                               (Chair: Lee D. Coraor, Penn State University)

Irina Chihaia and Thomas R. Gross (ETH Zurich)

Rong Xu and Zhiyuan Li (Purdue University)

R. Bonilla*, A. Sachedina, C. Zuzarte, P. Plachta, D. Jimenez-Gonzalez* and J.-L. Larriba-Pey* (Universitat Politecnica de Catalunya*, IBM Canada)

Timothy J. Dysart, Branden J. Moore, Lambert Schaelicke and Peter M. Kogge (University of Notre Dame)


12:00 - 1:30     Lunch


  1:30 - 2:20    Session 5: Java

                          (Chair: Mauricio Breternitz, Intel)

Wei Huang, Witawas Srisa-an* and J. Morris Chang (Iowa State University, University of Nebraska-Lincoln)

                    Mikhail Dmitriev (Sun Microsystems Laboratories)


2:20 - 2:45     Break


2:45 - 3:35     Session 6: Power Estimation and Reduction

                         (Chair: Jeanine Cook, NMSU)

Russ Joseph, Zhigang Hu* and Margaret Martonosi (Princeton University, IBM)

I. Kadayif, P. Nath, M. Kandemir and A. Sivasubramaniam (The Pennsylvania State University)

3:45 - 5:15     Panel Discussion

Quantitative evaluation of next-generation computer architectures and processor enhancements is possible only by running simulations. However, since the insights that are gained through simulation are predicated on the accuracy of the simulation results, and since the design decisions for future processor architectures -- which cost billions of dollars to design and implement -- are based on those insights, periodic examination of the simulation process becomes a necessity, rather than a luxury. Accordingly, this panel discusses the deficiencies of existing simulators, benchmarks, and simulation methodologies and techniques, and, in addition, what future directions are available for each.


Brad Calder, University of California, San Diego

Lieven Eeckhout, Ghent University

Lizy John, The University of Texas at Austin

Jim Smith, University of Wisconsin


David Lilja and Joshua Yi, Minnesota Supercomputing Institute, University of Minnesota

5:30 -                 Reception 



Day 3 - March 12 (Friday)




  9:00 - 12:30     Morning Session

          Lieven Eeckhout (Ghent University, Belgium)


Designing a high performance microprocessor is extremely time-consuming taking at least several years. An important part of this design effort is architectural simulation which defines the microarchitecture or the organization of the microprocessor. The reason why these simulations are so time-consuming is fourfold: (i) the architectural design space is huge, (ii) the number of benchmarks the microarchitecture needs to be evaluated with, is large, (iii) the number of instructions that need to be simulated per benchmark is huge as well, and (iv) simulators are becoming relatively slower due to the increasingly complex designs of current high performance microprocessors. In this tutorial, we will discuss these issues and propose a solution for each of them. As such, we will present an architectural simulation framework for designing high performance microprocessors which reduces the total simulation time by several orders of magnitude without sacrificing accuracy. This is done by combining several recently proposed techniques, such as statistical simulation, representative workload design using statistical data analysis techniques, trace sampling and reduced input sets.  



Lieven Eeckhout obtained his Master and PhD in Computer Science and Engineering from Ghent University, Belgium, in 1998 and 2002, respectively. He is currently working as a Postdoctoral Researcher at the same university through a grant from the Fund for Scientific Research—Flanders (FWO Vlaanderen). His research interests include computer architecture, performance evaluation and workload characterization. He has published numerous papers in various high quality journals (IEEE Computer, IEEE Micro and Journal of Instruction-Level Parallelism) and conferences (PACT, OOPSLA, etc.). 

12:30 -   2:00     Lunch


   2:00 -  5:30     Afternoon Session

          Wayne Wolf (Princeton University)


This tutorial will cover architectures and compilers for multimedia systems. Multimedia applications impose real-time constraints on continuous media; they also include a surprisingly wide variety of algorithms. Many multimedia systems also operate under power/energy constraints. As such, multimedia computing systems are an important area of interest for ISPASS. This tutorial will target individuals with experience in hardware and software but who have limited expertise in multimedia. We will start with an introduction to multimedia algorithms such as video and audio compression since the characteristics of these algorithms help to shape measurement strategies and architectural decisions. We will then cover modern multimedia architectures and compilation techniques relevant to those architectures. We will conclude with a case study drawn from our own research---the design of a multiprocessor system-on-chip for real-time gesture recognition. 



Wayne Wolf is professor of electrical engineering at Princeton University. Before joining Princeton, he was with AT&T Bell Laboratories, Murray Hill, New Jersey. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from Stanford University in 1980, 1981, and 1984, respectively. His research interests include embedded computing, VLSI systems, and multimedia information systems. He is author or co-author of over 250 technical publications. He is the author of Computers as Components and Modern VLSI Design (for which he won the ASEE/CSE and HP Frederick E. Terman Award). Wolf has been elected to Phi Beta Kappa and Tau Beta Pi. He is a Fellow of the IEEE and ACM and a member of the SPIE and ASEE.



For further information, please contact the Program or General Chairs:

Program Chair

Prof. Lizy John

Univ. of  Texas at Austin 

( )

General Chairs

Prof. Craig Chase

Univ. of Texas at Austin   

( )


Nasr Ullah


( )  


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