The 2004 IEEE International Symposium on Performance Analysis of Systems and Software is sponsored by the IEEE Computer Society's Technical Committee on Internet ,  Technical Committee on Computer Architecture , and Technical Committee on Microprogramming and Microarchitecture .

• The best paper awards were given to: 

  • "Dynamically Reducing Pressure on the Physical Register File through Simple Register Sharing", Liem Tran, Nicholas Nelson, Fung Ngai, Steve Dropsho and Michael Huang (University of Rochester)

  • "Deconstructing Commit", Gordon B. Bell and Mikko H. Lipasti (University of Wisconsin)

   

• Tutorials (March 12) will open to everyone with a conference registration. more

• Wireless networking is available on the conference site

ADVANCE PROGRAM

Day 1 - March 10 (Wednesday)

   8:00 -   9:00     Breakfast

    9:00 - 10:00     Opening and Keynote I   ( Yale Patt, The University of Texas at Austin )                              

• Title: Performance Analysis: A big plus, or an even bigger minus

Performance analysis can be one of the most important elements in the design cycle of a computer system. It can also be very important after the fact to influence future designs. But only if it is done right. If done wrong, it can be more harmful than if not done at all.

 

 (Chair: Lizy John, The University of Texas at Austin)

 

10:00 - 10:20     Break

10:20 - 12:00     Session 1: Benchmarking and Workload Characterization

                             (Chair: Ravi Bhargava, AMD)

• Eccentric and Fragile Benchmarks

Hans Vandierendonck and Koen De Bosschere (Ghent University, Belgium)

• Communication Breakdown: Analyzing CPU usage in Commercial Web Workloads

Jaidev P. Patwardhan, Alvin R. Lebeck and Daniel J. Sorin (Duke University)

• StatCache: A Probabilistic Approach to Efficient and Accurate Data Locality Analysis

Erik Berg and Erik Hagersten (Uppsala University, Sweden)

• Sockets Direct Protocol over InfiniBand in Clusters: Is it Beneficial?

 P. Balaji, S. Narravula, K. Vaidyanathan, S. Krishnamoorthy, J. Wu and D. K. Panda (The Ohio State University)

12:00 - 1:30     Lunch

  1:30 - 2:45     Session 2: Simulation

                           (Chair: Brian O'Krafka, Sun Microsystems)

• BlueGene/L Pseudo Cycle-accurate Simulator

Leonardo R. Bachega, Jose R. Brunheroto, Luiz DeRose, Pedro Mindlin and Jose E. Moreira (IBM Thomas J. Watson Research Center)

• A Co-Phase Matrix to Guide Simultaneous Multithreading Simulation

Michael Van Biesbrouck, Timothy Sherwood* and Brad Calder (University of California, San Diego, University of California, Santa Barbara*)

• Structures for Meta-Phase Classification

Jeremy Lau, Stefan Schoenmackers and Brad Calder (University of California, San Diego)

  2:45 - 3:15     Break

  3:15 - 4:30     Session 3: Architecture and Performance Evaluation

                           (Chair: Erik Altman, IBM)

• Deconstructing Commit

Gordon B. Bell and Mikko H. Lipasti (University of Wisconsin)

• Dynamically Reducing Pressure on the Physical Register File through Simple Register Sharing

Liem Tran, Nicholas Nelson, Fung Ngai, Steve Dropsho and Michael Huang (University of Rochester)

• Performance Evaluation of Exclusive Cache Hierarchies

Ying Zheng, Brian T. Davis and Matthew Jordan (Michigan Technological University)

Day 2 - March 11 (Thursday)

   8:00 -   9:00     Breakfast

    9:00 - 10:00     Keynote II ( Carl Anderson, IBM )

• Title: Information Technology Outlook

Projections of Information Technology (IT) future will be described. Forecasts of both hardware and software technology trends and ways in which those trends will come together to enable new uses and capabilities for IT. Important trends in key technologies such as raw computing speed, bandwidth, and storage and display capabilities will be shown. New technologies that have the potential of transforming the performance and characteristics of tomorrow's information processing systems and devices are explored.

 

(Chair: Nadeem Malik, IBM)

 

 10:00 - 10:20     Break

  10:20 - 12:00     Session 4: Memory and Caches

                               (Chair: Lee D. Coraor, Penn State University)

• Effectiveness of Simple Memory Models for Performance Prediction

Irina Chihaia and Thomas R. Gross (ETH Zurich)

• Using Cache Mapping to Improve Memory Performance of Handheld Devices

Rong Xu and Zhiyuan Li (Purdue University)

• Characterization of the data access behavior for TPC-C traces

R. Bonilla*, A. Sachedina, C. Zuzarte, P. Plachta, D. Jimenez-Gonzalez* and J.-L. Larriba-Pey* (Universitat Politecnica de Catalunya*, IBM Canada)

• Cache Implications of Aggressively Pipelined High Performance Microprocessors

Timothy J. Dysart, Branden J. Moore, Lambert Schaelicke and Peter M. Kogge (University of Notre Dame)

12:00 - 1:30     Lunch

  1:30 - 2:20    Session 5: Java

                          (Chair: Mauricio Breternitz, Intel)

• Adaptive Pretenuring for Generational Garbage Collection

Wei Huang, Witawas Srisa-an* and J. Morris Chang (Iowa State University, University of Nebraska-Lincoln)

• Selective Profiling of Java Applications Using Dynamic Bytecode Instrumentation

                    Mikhail Dmitriev (Sun Microsystems Laboratories)

2:20 - 2:45     Break

2:45 - 3:35     Session 6: Power Estimation and Reduction

                         (Chair: Jeanine Cook, NMSU)

• Spectral Analysis for Characterizing Program Power and Performance

Russ Joseph, Zhigang Hu* and Margaret Martonosi (Princeton University, IBM)

• Compiler-Directed Physical Address Generation for Reducing dTLB Power

I. Kadayif, P. Nath, M. Kandemir and A. Sivasubramaniam (The Pennsylvania State University)

3:45 - 5:15     Panel Discussion

• Topic: "The Future of Simulation: A Field of Dreams?"

Quantitative evaluation of next-generation computer architectures and processor enhancements is possible only by running simulations. However, since the insights that are gained through simulation are predicated on the accuracy of the simulation results, and since the design decisions for future processor architectures -- which cost billions of dollars to design and implement -- are based on those insights, periodic examination of the simulation process becomes a necessity, rather than a luxury. Accordingly, this panel discusses the deficiencies of existing simulators, benchmarks, and simulation methodologies and techniques, and, in addition, what future directions are available for each.

Panelists:

Brad Calder, University of California, San Diego

Lieven Eeckhout, Ghent University

Lizy John, The University of Texas at Austin

Jim Smith, University of Wisconsin

Moderators:

David Lilja and Joshua Yi, Minnesota Supercomputing Institute, University of Minnesota

5:30 -                 Reception 

Day 3 - March 12 (Friday)

TUTORIALS

  9:00 - 12:30     Morning Session

• Efficient Architectural Design of High Performance Microprocessors

          Lieven Eeckhout (Ghent University, Belgium)

Abstract:

Designing a high performance microprocessor is extremely time-consuming taking at least several years. An important part of this design effort is architectural simulation which defines the microarchitecture or the organization of the microprocessor. The reason why these simulations are so time-consuming is fourfold: (i) the architectural design space is huge, (ii) the number of benchmarks the microarchitecture needs to be evaluated with, is large, (iii) the number of instructions that need to be simulated per benchmark is huge as well, and (iv) simulators are becoming relatively slower due to the increasingly complex designs of current high performance microprocessors. In this tutorial, we will discuss these issues and propose a solution for each of them. As such, we will present an architectural simulation framework for designing high performance microprocessors which reduces the total simulation time by several orders of magnitude without sacrificing accuracy. This is done by combining several recently proposed techniques, such as statistical simulation, representative workload design using statistical data analysis techniques, trace sampling and reduced input sets.  

 

Biography: 

Lieven Eeckhout obtained his Master and PhD in Computer Science and Engineering from Ghent University, Belgium, in 1998 and 2002, respectively. He is currently working as a Postdoctoral Researcher at the same university through a grant from the Fund for Scientific Research—Flanders (FWO Vlaanderen). His research interests include computer architecture, performance evaluation and workload characterization. He has published numerous papers in various high quality journals (IEEE Computer, IEEE Micro and Journal of Instruction-Level Parallelism) and conferences (PACT, OOPSLA, etc.). 

12:30 -   2:00     Lunch

   2:00 -  5:30     Afternoon Session

• Architectures and Compilers for Multimedia

          Wayne Wolf (Princeton University)

Abstract: 

This tutorial will cover architectures and compilers for multimedia systems. Multimedia applications impose real-time constraints on continuous media; they also include a surprisingly wide variety of algorithms. Many multimedia systems also operate under power/energy constraints. As such, multimedia computing systems are an important area of interest for ISPASS. This tutorial will target individuals with experience in hardware and software but who have limited expertise in multimedia. We will start with an introduction to multimedia algorithms such as video and audio compression since the characteristics of these algorithms help to shape measurement strategies and architectural decisions. We will then cover modern multimedia architectures and compilation techniques relevant to those architectures. We will conclude with a case study drawn from our own research---the design of a multiprocessor system-on-chip for real-time gesture recognition. 

 

Biography: 

Wayne Wolf is professor of electrical engineering at Princeton University. Before joining Princeton, he was with AT&T Bell Laboratories, Murray Hill, New Jersey. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from Stanford University in 1980, 1981, and 1984, respectively. His research interests include embedded computing, VLSI systems, and multimedia information systems. He is author or co-author of over 250 technical publications. He is the author of Computers as Components and Modern VLSI Design (for which he won the ASEE/CSE and HP Frederick E. Terman Award). Wolf has been elected to Phi Beta Kappa and Tau Beta Pi. He is a Fellow of the IEEE and ACM and a member of the SPIE and ASEE.

 

 

For further information, please contact the Program or General Chairs:

This website is maintained by Univ. of Texas at Austin.

Contact Web Chair, if you have any questions.