Day 1

March 19 



Day 2

March 20


  8:00 -            Registration and Breakfast

  8:45 -  9:00  Welcome

  9:00 -10:00  Keynote I  (David Patterson, Univ. of California, Berkeley)

10:00 -10:30  Break

10:30 -12:00  Paper session 1

12:00 -  1:30  Lunch

  1:30 -  3:00  Paper session 2

  3:00 -  3:30  Break

Room A Room B
3:30 -  5:00  Paper session 3A  3:30 -  5:00  Paper session 3B
6:00 -            Reception 

Day 3

March 21


  8:00 -            Registration and Breakfast

  9:00 -10:00  Keynote II  (Mary Vernon, University of Wisconsin-Madison)

10:00 -10:30  Break

10:30 -12:00  Paper session 4 

12:00 -  1:30  Lunch

  1:30 -  3:00  Paper session 5 

  3:00 -  3:30  Break

Room A Room B

  3:30 -  5:00  Paper session 6A 

  3:30 -  5:00  Paper session 6B 



Day 1 - March 19 (Sunday)



Day 2 - March 20 (Monday)


    8:00 -                 Registration and Breakfast

    8:45 -   9:00      Welcome 

    9:00 - 10:00     Keynote I   (David Patterson, University of California, Berkeley)    


                               "RAMP: Research Accelerator for Multiple Processors - A Community Vision for a Shared Experimental Parallel HW/SW Platform"


10:00 - 10:30     Break


10:30 - 12:00     Session 1: Accelerating Simulation                           

                                             (Chair: Lieven Eeckhout, Ghent University)

12:00 - 1:30     Lunch


  1:30 - 3:00     Session 2: Microarchitecture Performance Evaluation

                               (Chair: Jim Bondi, Texas Instruments)

  3:00 - 3:30     Break


<<Parallel Session >>


  3:30 - 5:00     Session 3A: Statistical Models

                               (Chair: Krste Asanovic, MIT)

  3:30 - 5:00     Session 3B: Power

                               (Chair: Gabriel Loh, Georgia Institute of Technology)

6:00 -         Reception  (Foothills II Ballroom)



Day 3 - March 21 (Tuesday)


    8:00 -                 Registration and Breakfast

    9:00 - 10:00     Keynote II ( Mary Vernon, University of Wisconsin-Madison )                               


                              "Quantitative System Design"


 10:00 - 10:30     Break


 10:30 - 12:00     Session 4: Simulation Methodologies and Validation                      

                                  (Chair: Rajeev Balasubramonian, University of Utah)

12:00 - 1:30     Lunch


   1:30 -  3:00    Session 5: Caches and Prefetching             

                                (Chair: Charles Lefurgy, IBM)

3:00 - 3:30     Break


<<Parallel Session >>


 3:30 - 5:00    Session 6A: Workload Analysis

                             (Chair: Mikko Lipasti, University of Wisconsin)

  3:30 - 5:00    Session 6B: Simulators and Tools

                              (Chair: Annie Foong, Intel)

Keynote I 



The vast majority of computer architects believe the future of the microprocessor is hundreds to thousands of processors ("cores") on a chip. Given such widespread agreement, its surprising how much research remains to be done in algorithms, computer architecture, networks, operating systems, file systems, compilers, programming languages, applications, and so on to realize this vision. 


Fortunately, Moore's law has not only enabled dense multi-core chips, it has also enabled extremely dense FPGAs. Today, one to two dozen soft cores can be programmed into a single FPGA. With multiple FPGAs on a board and multiple boards in a system, 1000-processor designs can be economically and rapidly explored. To make this happen, however, requires a significant amount of infrastructure in hardware, software, and what we call "gateware", the register-transfer level models that fill the FGPAs. By using the Berkeley Emulation Engine boards that were created for other purposes, the hardware is already done. A group of architects plan to design the gateware, create this infrastructure, and share the results in an open-source fashion so that every institution could have their own.


Such a system would not just invigorate multiprocessors research in the architecture community. Since processors cores can run at 100 to 200 MHz, a large scale multiprocessor would be fast enough to run operating systems and large programs at speeds sufficient to support software research. Moreover, there is a new generation of FPGAs every 18 months with capacity for twice as many cores and run them faster, so future multiboard FPGA systems are even more attractive. Hence, we believe such a system would accelerate research across all the fields that touch multiple processors. Thus the acronymn RAMP, for Research Accelerator for Multiple Processors.


RAMP has the potential to transform the parallel computing community in computer science from a simulation-driven to a prototype-driven discipline, leading to rapid iteration across interfaces of the many fields of multiple processors, and thereby moving much more quickly to a parallel foundation for large-scale computer systems research in the 21st century.


The RAMP participants are Arvind (MIT), Krste Asanovic (MIT), Derek Chiou (UT Austin), James C. Hoe (CMU), Christoforos Kozyrakis (Stanford), Shih-Lien Lu (Intel), Mark Oskin (U Washington), David Patterson (UC Berkeley, Co-Principle Investigator), Jan Rabaey (UC Berkeley), and John Wawrzynek (UC Berkeley, Principle Investigator). We hope to have systems available for others to acquire in a year or two.


Biographical sketch 


David A. Patterson has been Professor of Computer Science at the University of California, Berkeley since 1977. He is one of the pioneers of both RISC and RAID, both of which are widely used. He co-authored five books, including two on computer architecture with John Hennessy. Past chair of the Computer Science Department at U.C. Berkeley and the Computing Research Association, he was elected President of the Association for Computing Machinery (ACM) for 2004 to 2006 and served on the Information Technology Advisory Committee for the U.S. President from 2003 to 2005.


His work was recognized by education and research awards from ACM and IEEE and by election to the National Academy of Engineering. In 2005 he shared Japan's Computer & Communication award with Hennessy and was named to the Silicon Valley Engineering Hall of Fame.

Keynote II 



This talk will provide a 20-year perspective on the use of analytic models to design of a wide range of commercially important architectures and systems with complex behavior. These systems include resources with highly bursty and/or correlated packet arrivals, communication protocols with complex routing and blocking of messages, resources that are configured for a very high probability (e.g., 0.9999) of providing immediate service to each arriving client, and complex large-scale Grid/Internet applications. The examples illustrate some guiding principles for model development, and show that the models can be relatively easy to develop. More importantly, the models can be highly accurate -- often more accurate than simulation, and sometimes more accurate than the system implementation! The examples also illustrate that the models can provide unique insight into system design as well as significant new system functionality. In other words, analytic models are a key tool for competitive systems engineering. Time permitting, the talk will include some important observations about workload models, and some ways to avoid key pitfalls in simulation.


Biographical sketch 


Mary K. Vernon received a B.S. degree with Departmental Honors in chemistry and the Ph.D. degree in computer science from the University of California at Los Angeles. In 1983 she joined the Computer Science Department at the University of Wisconsin-Madison, where she is currently Professor of Computer Science and Industrial Engineering. Her research interests include performance analysis techniques for evaluating high performance computer/communication system design tradeoffs, parallel and distributed architectures and applications, computer system security, Internet transport protocols, network traffic analysis, workload characterization, optimized CMP hardware/software co-design, and storage system design. She has co-authored over 80 technical papers including seven award papers - such as one of three "fast track to ToN" papers at Infocom 2004, and the Best Paper Award at the 2005 USENIX Security Symposium. Prof. Vernon has served on the editorial board of the IEEE Transactions on Parallel and Distributed Systems, the 1999 NSF Blue Ribbon Panel for High Performance Computing, the NSF CISE Advisory Board, the CRA Board of Directors, the Board of Directors of the NCSA, and as Chair of the ACM SIGMETRICS. She received the NSF Presidential Young Investigator Award in 1985, the ACM Fellow award in 1996, the UW-Madison Vilas Associate Award in 2000 and the UW-Madison Kellett Mid-career Award in 2006. She is a member of the IFIP WG 7.3 on Information Processing System Modeling, Measurement and Evaluation.
















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