Day 1

April 25 



Day 2

April 26


  8:00 -            Registration

  8:45 -  9:00  Welcome

  9:00 -10:00  Keynote I  (Don Newell, Intel Corporation)

10:00 -10:30  Break

10:30 -12:00  Session 1

12:00 -  1:30  Lunch

  1:30 -  3:30  Session 2

  3:30 -  4:00  Break

Room A Room B
4:00 -  5:00  Session 3A  4:00 -  5:00  Session 3B
6:00 -            Reception  (Santa Clara Foyer)

Day 3

April 27


  8:00 -            Registration

  9:00 -10:00  Keynote II  (Leslie Barnes, AMD)

10:00 -10:30  Break

10:30 -12:00  Session 4 

12:00 -  1:30  Lunch

Room A Room B

  1:30 -  3:00  Session 5A 

   3:00 -  3:30  Break

   3:30 -  4:30  Session 6A 

  1:30 -  3:00  Session 5B 

   3:00 -  3:30  Break

   3:30 -  4:30  Session 6B 



Day 1 - April 25 (Wednesday)



Day 2 - April 26 (Thursday)


    8:00 -                 Registration

    8:45 -   9:00      Welcome 

    9:00 - 10:00     Keynote I   (Don Newell, Intel Corporation)    


                               "Workloads, Scalability, and QoS Considerations in CMP Platforms( pdf )


10:00 - 10:30     Break


10:30 - 12:00     Session 1: Simulators/Simulation Methodology                           

                                             (Chair: Leslie Barnes, Advanced Micro Devices)

12:00 - 1:30     Lunch


  1:30 - 3:30     Session 2: Application Characterization

                               (Chair: Tao Li, University of Florida)


  3:30 - 4:00     Break


<<Parallel Session >>


  4:00 - 5:00     Session 3A: Simulation Sampling I

                               (Chair: Ravishankar Iyer, Intel)

  4:00 - 5:00     Session 3B: Prefetching

                               (Chair: Mainak Chaudhuri, Indian Institute of Technology, Kanpur)

6:00 -         Reception  (Santa Clara Foyer)



Day 3 - April 27 (Friday)


    8:00 -                 Registration

    9:00 - 10:00     Keynote II ( Leslie Barnes, AMD )                               


                              "Performance Modeling and Analysis for AMD's High Performance Microprocessors( pdf )


 10:00 - 10:30     Break


 10:30 - 12:00     Session 4: Performance Models and Phase Classification                      

                                  (Chair: Nasr Ullah, Freescale Semiconductor)


12:00 - 1:30     Lunch


<<Parallel Session >>


   1:30 -  3:00    Session 5A: Power and Reliability             

                                (Chair: Rajeev Balasubramaniam, University of Utah)


   1:30 -  3:00    Session 5B: Simulation Sampling and Performance Prediction     

                                (Chair: Paolo Faraboschi, HP Labs)


3:00 - 3:30     Break


<<Parallel Session >>


 3:30 - 4:30    Session 6A: Evaluating Real Systems

                             (Chair: Russ Joseph, Northwestern University)

  3:30 - 4:30    Session 6B: Memory Systems

                              (Chair: Yefim Shuf, IBM Watson Research Center)


Keynote I 


We have entered the CMP era and are continuously accelerating the pace at which more cores are integrated on the same die. It is now possible to imagine building a 32-core CMP platform in the near future. To make best use of these cores, the workload scenarios are also evolving rapidly. For example, consolidation via virtualization is a rapidly growing phenomenon in the server marketplace. In this talk, we will start by describing our vision of large-scale CMP platforms and future workload scenarios over the next decade. We will then re-visit the typical performance requirements and behavior of these platforms. Based on analysis of several commercial server workloads running individually, we will demonstrate platform scalability considerations. Based on simultaneous execution of heterogeneous workloads, we will show platform quality of service considerations. The intent is to describe the opportunities and challenges that 2015 CMP platforms will face and discuss potential solutions that need further research.

Biographical sketch 

Donald Newell is a Sr. Principal Engineer in Intel's Systems Technology Lab. He has spent most of his career working on networking and systems software for server platforms and real-time systems. Don has worked on a number of emerging technologies at Intel. This includes leading the group that developed Intel's frameworks for media streaming over the Internet and to support data broadcast for DTV. Don chaired the Advanced Television System Committee (ATSC) work on data broadcast in DTV and was a co-author of IETF RFC 2429. Don and his group were also key contributors to the recently announced Intel(r) I/O Acceleration Technology (Intel(r) I/OAT). Currently, he leads a group working on Platform QoS with an emphasis on large-scale CMP architectures.


Keynote II 



This talk will cover performance modeling and analysis at AMD, directed at our X86-64 processor development. Topics covered will include benchmark analysis and workload development for simulation, and simulation tools and methodologies used for power/performance analysis of our next generation of microprocessors.


Biographical sketch 

Leslie Barnes joined Advanced Micro Devices in 2001 and manages the Performance and Simulation team for the Sunnyvale Design Center, with responsibilities for the current Athlon64 and Opteron processor modeling and also a new design currently on the drawing boards. Prior to this he worked at HAL computer systems, a Fujitsu Subsidiary, and eventually ended up leading a team building simulators and doing performance analysis for a next-generation Sparc64 based server processor. Leslie has a PhD in Theoretical Chemistry from the University of Western Australia, and has held an NRC Fellowship at NASA Ames Research Center in Mountain View, California, and a Visiting Scientist Fellowship at the IBM Almaden Research Center in San Jose, California.
















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