Day 1 -- March 29

Full-Day Workshop

Morning Workshop

Morning Tutorial

Afternoon Tutorial

DSM 2015 - Tutorial on Datacenter Simulation Methodologies

Day 2 -- March 30

9:30-10:50 Session I: Best Paper Candidates, Session Chair: Jose Renau, UC Santa Cruz

9:30-9:50: Critical-Path Candidates: Scalable Performance Modeling for MPI Workloads
J. Chen, R. Clapp
9:50-10:10: DELPHI: A Framework for RTL-Based Architecture Design Evaluation Using DSENT Models
M. Papamichael, C. Cakir, C. Sun, O. Chen, J. Hoe, K. Mai, L. Peh, V. Stojanovic
10:10-10:30: Where Does the Time Go? Characterizing Tail Latency in Memcached
G. Blake, A. Saidi
10:30-10:50: Micro-Architecture Independent Analytical Processor Performance and Power Modeling
S. Van den Steen, S. De Pestel, M. Mechri, S. Eyerman, T. Carlson, L. Eeckhout, E. Hagersten, D. Black-Schaffer

11:15-11:35: Graph processing platforms at scale: practices and experiences
S. Lim, S. Lee, G. Ganesh, T. Brown, S. Sukumar
11:35-11:55: Graph-Matching-Based Simulation-Region Selection for Multiple Binaries
C. Yount, H. Patil, M. Islam, A. Srikanth

1:20-2:20 Session III: Sampling, Session chair: Stijn Eyerman, Ghent University

1:20-1:40: A Modeling Framework for Reuse Distance-based Estimation of Cache Performance
X. Pan, B. Jonsson
1:40-2:00: Multi-Program Benchmark Definition
A. Jacobvitz, A. Hilton, D. Sorin
2:00-2:20: Precise Computer Performance Comparisons Via Statistical Resampling Methods
B. Li, S. Chen, L. Peng

2:45-3:05: PairMiner: mining for paired functions in kernel extensions
H. Liu, B. JiaJu, Y. Wang, S. Hu
3:05-3:25: Self-monitoring Overhead of the Linux perf_event Performance Counter Interface
V. Weaver
3:25-3:45: Hierarchical Cycle Accounting: A new method for application performance tuning
A. Nowak, D. Levinthal, W. Zwaenepoel

3:45-4:45 Session V: Insights, Session chair: Andrew Hilton, Duke University

3:45-4:05: Revisiting Symbiotic Job Scheduling
S. Eyerman, P. Michaud, W. Rogiest
4:05-4:25: Micro-Architecture Independent Branch Behavior Characterization
S. De Pestel, S. Eyerman, L. Eeckhout
4:25-4:45: Non-Volatile Memory Host Controller Interfaces Performance Analysis in High-Performance I/O Systems
A. Awad, B. Kettering, Y. Solihin

8:00-9:00 Keynote II: Andreas Olofsson, What I Learned Building a Parallel Processor from Scratch

9:10-10:30 Session VI: Synthesizable and GPUs: Andrew Hilton, Duke University

9:10-9:30: Nyami: Synthesizable GPU Architectural Model for General-Purpose and Graphics-Specific Workloads
J. Bush, P. Dexter, T. Miller, A. Carpenter
9:30-9:50: DRAW: Investigating Benefits of Adaptive Fetch Group Size on GPU
M. Yoon, Y. Oh, S. Lee, S. Kim, D. Kim, W. Ro
9:50-10:10: DNOC: An Accurate and Fast Virtual Channel and Deflection Routing Network-On-Chip Simulator
G. Oxman, S. Weiss
10:10-10:30: Performance Evaluation of a DySER FPGA Prototype System Spanning the Compiler, Microarchitecture, and Hardware Implementation
C. Ho, V. Govindaraju, T. Nowatzki, R. Nagaraju, Z. Marzec, P. Agarwal, C. Frericks, R. Cofell, K. Sankaralingam

10:55-11:55 Session VII: Mobile, Session chair: Mark Hempstead, Drexel University

10:55-11:15: Mosaic: Cross-Platform User-Interaction Record and Replay for the Fragmented Android Ecosystem
M. Halpern, Y. Zhu, R. Peri, V. Reddi
11:15-11:35: A Study of Mobile Device Utilization
C. Gao, A. Gutierrez, M. Rajan, R. Dreslinski, T. Mudge, C. Wu
11:35-11:55: Full-System Approach to Analyze the Impact of Next-Generation Mobile Flash Storage
R. de Jong, A. Hansson

1:20-2:40 Session VIII: Emulation/Simulation, Session chair: Benjamin C. Lee, Duke University

1:20-1:40: QTrace: An Framework for Customizable Full System Instrumentation
X. Tong, A. Moshovos
1:40-2:00: Pydgin: Generating Fast Instruction Set Simulators from Simple Architecture Descriptions with Meta-Tracing JIT Compilers
D. Lockhart, B. Ilbeyi, C. Batten
2:00-2:20: Reciprocal Abstraction for Computer Architecture Co-Simulation
M. Moeng, R. Melhem, A. Jones
2:20-2:40: SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation
S. Nilakantan, K. Sangaiah, A. More, G. Salvador, B. Taskin, M. Hempstead

3:05-4:45 Session IX: Real Hardware, Session chair: Vince Weaver, University of Maine

3:05-3:25: Performance and Energy Evaluation of Data Prefetching on Intel Xeon Phi
D. Guttman, M. Kandemir, M. Arunachalam, V. Calina
3:25-3:45: Emulating Cache Organizations on Real Hardware Using Performance Cloning
Y. Wang, Y. Solihin
3:45-4:05: Prometheus: Scalable and Accurate Emulation of Task-Based Applications on Many-Core Systems
G. Kestor, R. Gioiosa, D. Chavarria
4:05-4:25: Analyzing Communication Models for Distributed Thread-Collaborative Processors in Terms of Energy and Time
B. Klenk, L. Oden, H. Froening
4:25-4:45: Characterization and analysis of a Web Search benchmark
Z. Hadjilambrou, M. Kleanthous, Y. Sazeides