A new generation of computing devices is emerging. We envision a world where computing will expand from business and personal uses to be present everywhere: in our cars, in the lighting system of a city, in our shoes, and in the clothes we wear just to name a few. These devices will consist of multiple computing elements, with a few being general purpose but many of them will be specialized in certain computing domains. They will be interconnected and interoperable to leverage their specialization and the complementary information that each one will gather. A key feature of many of these devices will be their ability to understand the world around them and provide real time responses in complex situations, emulating human perception and problem solving. In this talk we will discuss this trend and some of the research areas that will be key to make this vision happen.
Bio: Antonio Gonzalez received his Ph.D. degree from the Universitat Politecnica de Catalunya (UPC), in Barcelona, Spain, in 1989. He joined the faculty of the Computer Architecture Department of UPC in 1986 and became a Full Professor in 2002. He was the founding director of the Intel Barcelona Research Center from 2002 to 2014.
His research has focused on computer architecture. In this area, Antonio holds over 40 patents, has published over 300 research papers and has given over 100 invited talks. He has also made multiple contributions to the design of the architecture of several Intel processors.
Antonio has been program chair for ICS 2003, ISPASS 2003, MICRO 2004, HPCA 2008 and ISCA 2011, and general chair for MICRO 2008 and HPCA 2016 among other symposia. He has served on the program committees for over 100 international symposia in the field of computer architecture, and as an Associate Editor of the IEEE Transactions on Computers, IEEE Transactions on Parallel and Distributed Systems, IEEE Computer Architecture Letters, ACM Transactions on Architecture and Code Optimization, ACM Transactions on Parallel Computing, and Journal of Embedded Computing.
Antonio’s awards include the award to the best student in computer engineering in Spain graduating in 1986, the 2001 Rosina Ribalta award as the advisor of the best PhD project in Information Technology and Communications, the 2008 Duran Farrell award for research in technology, the 2009 Aritmel National Award of Informatics to the Computer Engineer of the Year, the 2013 King James I award for his contributions in research on new technologies, and the 2014 ICREA Academia Award. He is an IEEE Fellow.
Performance analysis and modeling is of critical importance to computer systems and architecture research and development. We must design and build our simulators, benchmarks, and analysis tools correctly, and we must measure and analyze our results rigorously, otherwise experimental research and development may lead to incorrect and misleading conclusions and ineffective optimizations. These tools are critical to our understanding of both the problems and the solutions. In this talk, I will revisit the importance of rigorous performance evaluation, and decompose the performance evaluation challenge into two sub-problems, experimental design and data analysis. I will discuss some of the (not so obvious) pitfalls in both experimental design and data analysis, and argue for potential solutions. Along the way, I will remind ourselves why we are doing performance analysis in the first place.
Bio: Lieven Eeckhout is a Professor at Ghent University, Belgium, where he is currently leading a research group with 7 PhD students and 2 postdoctoral researchers. He received his PhD in Computer Science and Engineering from Ghent University in 2002, and he has over 15 years of academic experience in computer architecture research, with a specific emphasis on performance evaluation and modeling. He published more than 150 papers at premier and high-quality venues in the field. His work was awarded with two IEEE Micro Top Pick selections (2007 and 2010); the ISPASS 2013 Best Paper Award; and Best Paper Nominations at PACT 2004, and ISPASS 2012 through 2016. He served as program chair for HPCA 2015, CGO 2013 and ISPASS 2009, and general chair for ISPASS 2010. He is the current editor-in-chief of IEEE Micro (as of Jan 2015), and associate editor of IEEE Computer Architecture Letters, IEEE Transactions on Computers, and ACM Transactions on Architecture and Code Optimization.
As transistor sizes continue to scale, we are about to witness stunning levels of chip integration, with 1,000 cores on a single die, and increasing levels of 3D stacking. In these architectures, energy and power will constrain the designs even more than they do today. In this context, this talk presents some of the technologies that we may need to deploy to provide very high energy efficiency. We will need Voltage-Scalable cores--i.e., flexible cores that can competitively operate both at high and low voltage ranges, unlike existing big-little designs. Extensive power gating will be crucial, likely with the help of non-volatile memory. Further, to avoid energy waste, we will need power-management controllers that use control-theoretic techniques for maximum energy efficiency. New, more energy efficient devices will also gradually replace CMOS as we know it. A combination of all of these techniques--and more--will be needed.
Bio: Josep Torrellas is a Professor of Computer Science and Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. He is a Fellow of IEEE and ACM. He is the Director of the Center for Programmable Extreme-Scale Computing, a center focused on architectures for extreme energy and power efficiency. He was until recently the Director of the Intel-Illinois Parallelism Center (I2PC), a center created by Intel to advance parallel computing. He has made contributions to parallel computer architecture in the areas of shared memory multiprocessor organizations, cache hierarchies and coherence protocols, thread-level speculation, and hardware and software reliability. He received the 2015 IEEE CS Technical Achievement Award.