Shared memory provides the basis for communication and synchronization on multicore CPUs, single- and multi-GPU systems, and many programming languages. Unfortunately, many people already consider the lingua franca among components, the memory consistency model, to be somewhat unintelligible. How will we adapt to a future where compute units become even more complex and heterogeneous? How should we incorporate new storage technologies into the memory hierarchy? How will we account for the increasing non-uniformity introduced by packaging technologies such as multi-chip modules and die stacking? This talk will explore how to design memory architectures capable of seamlessly incorporating all of these diverse features. First, we will study the performance targets and the bottlenecks faced by large-scale memory systems such as those within multi-GPU platforms. Then, we will explore the motivations behind the complex wording used in ISA and language memory model specifications within industry, as well as the state of topics such as scopes and persistency. Finally, we will look at the implications of these new features and constraints on both accelerators and general-purpose software.
Dan Lustig is a Senior Research Scientist in NVIDIA's Architecture Research Group. His work mainly focuses on memory consistency models, virtual memory, and GPU architecture. His research has been highlighted by five selections and three honorable mentions in IEEE Micro's Top Picks as well as three nominations for Best Paper at MICRO. He is also active in the development of RISC-V, having served as chair of the Memory Model and Virtual Memory Task Groups. For the former, he received the inaugural RISC-V Foundation Board of Directors Award in 2018. Dan received a BSE from the University of Pennsylvania in 2009 and a PhD from Princeton University in 2015.
This website is maintained by the ISPASS-2021 Committee.
Contact Andreas Diavastos if you have any questions or comments on this website.