WORKSHOP on UNIQUE CHIPS and SYSTEMS (UCAS-1)

To be held in conjunction with IEEE International Symposium on Performance  Analysis of Systems and Software (ISPASS05)

March 20, 2005

Hotel Renaissance

Austin, Texas

ADVANCE PROGRAM

8:00 -                 Registration and Breakfast

8:30 -   8:40     Opening Remarks

          General Chair: Eugene John, University of Texas at San Antonio

          Co-Chair : Juan Rubio, ARL IBM

8:40 - 10:10     Session 1: Emerging Chips and Applications

                           (Chair: Fred Hudson, University of Texas)

• Extended Analog Computers: A Unifying Paradigm for VLSI, Plastic and Colloidal Computing Systems
  Jonathan W. Mills, Bryce Himebaugh, Andrew Allred, Daniel Bulwinkle, Nathan Deckard, Natarajan Gopalakrishnan, Joel Miller, Tess Miller, Kota Nagai, Jay Nakamura, Bayo Ololoweye, Radu Vlas, Philip Whitener, Myint Ye, and Chen Zhang 
  (Indiana University)

• Visualization by Subdivision: Two Applications for Future Graphics Platforms
  Chand T. John 
  (Stanford University)

•  Invited Paper: Integrated High Performance Security in a x86 Processor
  Glenn Henry, President, Centaur Technology Inc.

10:10 - 10:30     Break

10:30 - 12:00     Session 2: Low Power

                             (Chair: Juan Rubio, IBM)

• Trace-Based Energy Reduction for Low-Power Microprocessor Design
  Xia Xiaoxin, Tay Teng Tiow 
  (National University of Singapore)

• Alleviating Thermal Constraints while Maintaining Performance Via Silicon-Based On-Chip Optical Interconnects
  Nicholas Nelson, Gregory Briggs, Mikhail Haurylau, Guoqing Chen, Hui Chen, David H. Albonesi, Eby G. Friedman, Philippe M. Fauchet 
  (University of Rochester and Cornell University) 

• Power Management in RAID Server Disk System Using Multiple Idle States
  Hogil Kim, Eun Jung Kim and Rabi N. Mahapatra 
  (Texas A & M University)

 12:00 - 1:00     Lunch

   1:00 -  2:00    Keynote ( Peter Hofstee , IBM )    

• Title: Aspects of the Cell Processor

  2:00 - 3:00     Session 3: Memory and Arithmetic

                           (Chair: Fred Hudson, University of Texas)

• Micro-threaded Row and Column Operations in a DRAM Core
  Frederick A. Ware and Craig Hampel 
  (Rambus, Inc)

• A Library of Low-Cost High-Performance Multipliers Using Borrow Parallel Counters and Double-Triple expansion Schemes
  Rong Lin (SUNY Genesco) and Ronald B. Alonzo (University of Rochester)
  

   3:30 - 3:50     Break

   3:50 -  5:20     Session 4: Multiprocessors

                             (Chair: Juan Rubio, IBM)

• A High Performance, Low Power Chip Multiprocessor for Large Scale Molecular Orbital Calculation
  K. Nakamura, H. Honda, K. Inoue,(Kyushu University), H. Sato, M. Uehara, H.Komatsu (Seiko Epson Corp.), H. Umeda, Y. Inadomi, U. Nagashima (National Institute of Advanced Industrial Science and Technology), K. Araki, T. Sasaki (A Priori Microsystems Inc.), S. Obara (Hokkaido University of Education), K. Murakami (Kyushu University)

• A Processor With Dual Thread Execution Models
  Rania Mameesh and Manoj Franklin 
  (University of Maryland)

• A method for reducing energy waste in barrier spinloops for shared-memory multiprocessors in LASeR hardware
  Dipnarayan Guha and Qonita Muhammad Shahab 
  (Researchers, Information and Communication University, Republic of Korea)

  5:20 - 5:30     Closing Remarks

Keynote

• Aspects of the Cell Processor
  Peter Hofstee , IBM

Abstract

The Cell processor is a first implementation of a new class of processors aimed at compute intensive game, media and broadband applications. This talk will place the design in the context of a new set of demands placed on processors by focusing on a microprocessor as defined by its response to the user and the network.

 

Biographical sketch 

Peter Hofstee received his Ph.D. in computer science from Caltech in 1995. In 1995 and 1996 he was on the faculty at Caltech. In 1996 he joined the IBM Austin Research Laboratory where he worked on the world's first 1GHz CMOS integer microprocessor (ISSCC 1998). In 2001 Dr. Hofstee was one of the founding members of the joint Sony-Toshiba-IBM design center in Austin to develop the next generation of microprocessors for the broadband era.

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