WORKSHOP on UNIQUE CHIPS and SYSTEMS (UCAS-2)
To be held in conjunction with IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS06)
March 19, 2006
9:15 - 9:45 Registration
9:45 - 10:00 Welcome
10:00 - 11:00 Keynote (Stephen W. Keckler, UT-Austin)
11:00 - 12:00 Session 1: FPGAs and FPGA Based Systems
High Throughput Self-Timed FPGA Core Architecture
of Delay Queues for a Ravenscar Hardware Kernel
Gustaf Naeser, Kristina Lundqvist, Massachusetts Institute of Technology and Johan Furunas, Malardalen University, Sweden
12:00 - 1:30 Lunch
1:30 - 3:30 Session 2: Novel Architectures
Lazy Instruction Prediction to Reduce Processor Wakeup Power Dissipation
Continuation-model-based Multi-threading Processor
Masaaki Izumi , Satoshi Amamiya, Matsuzaki Takanori, and Makoto Amamiya;
Error Correction for On-chip Interconnection Networks
P. Bhojwani, R. Singhal, G. Choi, R. Mahapatra;
: a Zero Timing Overhead Power-Aware BTB for High-Performance Processors
Kaveh Deris and Amirali Baniasadi;
3:30 - 4:00 Break
4:00 - 5:30 Session 3: Workload Analysis
of Wavefront Algorithms on Large-scale Two-level Heterogeneous Processing
Adolfy Hoisie and Darren Kerbyson,
Based Power Phase Analysis of a Commercial Workload
Characteristics and Implications of Alignment of Multiple Bioinformatics
Lan Luo, Tao Li and Tamer Kahveci; Universtiy of
Computer architects have reached a crossroads. While conventional architectures have benefited greatly from reduced feature sizes, they have reached their performance limits. In addition to the power wall, clock rates will not increase at recent historic rates and conventional processors do no better at exploiting concurrency than they did in 1998. As a result, industry has abandoned the goal of improving uniprocessors and shifted efforts toward chip multiprocessors. TRIPS is a unique architecture that seeks to better exploit uniprocessor-level concurrency by changing the way instruction-level concurrency is expressed to the hardware, thereby extending the scaling of uniprocessors and enabling more efficient multiprocessors.
In this talk, I will discuss the TRIPS processor architecture and microarchitecture, which is designed to extract concurrency from serial workloads and to be scalable into future nanoscale technologies. In particular, I will describe the explicit datagraph execution (EDGE) instruction set architecture of TRIPS and how it efficiently encodes concurrency in its dataflow execution model. I will also discuss how the TRIPS microarchitecture is partitioned for scalability and how it implements deep speculation and latency tolerance. EDGE architectures can support out-of-order windows of thousands of instructions with little difficulty and less design complexity than conventional superscalar architectures. Finally, I will describe the TRIPS prototype implementation which will be operational in the laboratory in Summer, 2006.
Stephen W. Keckler is an Associate Professor of Computer Sciences and Electrical and Computer Engineering at UT-Austin. His research interests include computer architecture, parallel and embedded processors, VLSI design, adaptive computing, and the influence of technology trends on computer system design. With Doug Burger, he currently co-leads the TRIPS project which is developing and prototyping high performance adaptive computer systems. Dr. Keckler has received an NSF CAREER award, multiple IBM Faculty Fellowship awards, and the 2003 ACM Grace Murray Hopper award; he is also an Alfred P. Sloan Foundation Research Fellow. He holds a BS in electrical engineering from Stanford University and an MS and a PhD in computer science from the Massachusetts Institute of Technology.
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