WORKSHOP on UNIQUE CHIPS and SYSTEMS (UCAS-3)

To be held in conjunction with IEEE International Symposium on Performance  Analysis of Systems and Software (ISPASS07)

April 25, 2007

Hilton San Jose

San Jose, California, USA

 

ADVANCE PROGRAM

9:15 -     9:45     Registration

9:45 -   10:00     Welcome

 

10:00 - 11:00    Keynote: Reconfigurable Asynchronous Logic

                                                Rajit Manohar, Computer Systems Lab, Cornell University

 

11:00 -  12:00     Session 1:

                             

     Scientific Algorithms: Performance, Power, Thermal Properties on Modern Computing Architectures
 I. Lee, Troy University and P. Raghavan, Pennsylvania State University

 

     Design of a Hardware-Cryptography-Embedded Processor for Pervasive Computing
Masa-aki Fukase  and Tomoaki Sato; Hirosaki University , Hirosaki , Japan

 

12:00 - 1:30     Lunch

 

1:30 - 3:00     Session 2:

                           

 

     Mapping of Applications to Heterogeneous Cores Based on Micro-architecture Independent Characteristics
Jian Chen, Nidhi Nayyar, Lizy K.John; University of Texas at Austin

 

     Exploiting Value Similarity for Soft Error Tolerance
 Joonhyuk Yoo and Manoj Franklin; University of Maryland

 

     Rotated Array Clustered Extended Hypercube Processor, the RACE-H Processor  

       Gerald G. Pechanek, Lightning Hawk Consulting; Mihailo Stojancic,ViCore Technologies; Frank Barry, Onward Communications; and Nikos Pitsianis, Duke University

   

   3:00 - 3:30     Break

 

   3:30 - 5:00     Session 3:

                           

     Maximizing Sharing by using Different L2-Cache Sizes in in-order Multi-Cores
 Mario Donato Marino - University of Sao Paul

 

     Efficient Modeling for the Analysis of Ultra Wide Band Technology for High Data Rate

Ahmed Ebaid, Khalil Shujaee and Roy George; Clark Atlanta University

 

     Hardware Support for Managed Code
Prabuddha Ghosh, AMD, Austin , Texas

 

 

 

 

 

 


Keynote: Reconfigurable Asynchronous Logic

                 Rajit Manohar, Computer Systems Lab, Cornell University

 

Abstract

 Post-silicon configurability is becoming more and more attractive for a variety of reasons. Design tuning to compensate for variations, instrumentation for debugging and performance monitoring, and field-upgradeability to support a variety of standards and to change functionality are some of the reasons reconfigurable logic is gaining in importance. The high cost of custom chip design also makes it difficult to justify the cost if a reconfigurable solution is a viable alternative.  

A field-programmable gate array (FPGA) consists of an array of programmable blocks and programmable interconnect that can be used to implement arbitrary logic. The original logic specified using a hardware description language (typically Verilog or VHDL) is synthesized and mapped to the underlying programmable fabric. Modern FPGAs can implement designs containing the equivalent of millions of gates, enabling relatively large designs to be implemented using a reprogrammable solution.

 Asynchronous logic is a way to design circuits that do not use global clocks for synchronization. Global synchronization is replaced by local handshaking, and a variety of circuit styles and protocols have been developed that implement different styles of asynchronous logic. The elimination of the global clock and the irregularity of designs mapped to FPGAs makes asynchronous logic an attractive method for implementing reconfigurable systems.

 Mapping any logic family to an FPGA requires meeting any timing constraints required for correct operation to be met after the design is mapped, and placed and routed on the underlying FPGA architecture. When mapping asynchronous logic to an FPGA, this can be challenging because of the complexities of the timing requirements for correct operation. Most asynchronous circuit families require control signals to be hazard-free, and therefore logic mapping is a harder problem than in the synchronous case. Routing can be challenging because some asynchronous signals require relative delay assumptions on fan-out for correct operation.

To avoid these basic issues, we have developed a new asynchronous FPGA architecture that is capable of implementing high-performance asynchronous logic. The architecture is based on common building blocks found in high-performance asynchronous pipelines. Reconfigurability is introduced to change the functions computed by the pipeline elements, and to change the connections between the elements. By using a higher lever of abstraction for the FPGA, we avoid the problems that have plagued previous asynchronous FPGA designs. The architecture supports standard logic optimization techniques, as well as conventional place-and-route algorithms.

We describe a variety of benchmarks and their performance on the architecture, discussing the benefits and limitations of this class of asynchronous FPGAs.

Brief Biography:

Rajit Manohar is an Associate Professor of Electrical and Computer Engineering at Cornell University , where his group conducts research on asynchronous design. He received his B.S. (1994), M.S. (1995), and Ph.D. (1998) in Computer Science from the California Institute of Technology, and has been a member of the Cornell faculty since 1998 where he co-founded its Computer Systems Laboratory. He is the receipient of an NSF CAREER award, two best paper awards, five teaching awards, and was named to MIT technology review's top 35 young innovators under 35 (2005).  He was one of the principal designers of MiniMIPS, the first high-performance asynchronous microprocessor. His group has developed several asynchronous VLSI systems, including the first microprocessor for sensor networks, an event-based chip-multiprocessor, and a pipelined FPGA.