WORKSHOP on UNIQUE CHIPS and SYSTEMS (UCAS-4)

To be held in conjunction with IEEE International Symposium on Performance  Analysis of Systems and Software (ISPASS08)

April 20, 2008

Austin, Texas, USA

 

ADVANCE PROGRAM

9:15 -     9:45     Registration

9:45 -   10:00     Welcome

 

10:00 - 11:00    Keynote:   Dynamic Synthesis for Processor Overlays

                             Doug Burger, Department of Computer Science, University of Texas at Austin

 

11:00 -  12:00     Session 1:

                             

     A Vacuum Microelectronic Freespace Crossbar
 
Michel Victor, Aris Silzars, Exaconnect Inc. and Edward Davidson, University of Michigan

 

     The Architecture of an Extended Analog Computer Core
Jonathan Mills, Indiana University

 

12:00 - 1:30     Lunch

 

1:30 - 3:00     Session 2:

                           

 

     Optimizing Issue Queue Reliability to Soft Error on Simultaneous Multithread Architectures
Xin Fu, Wangyuan Zhang, Tao Li, Jose Fortes, University of Florida

 

     Performance Analysis of Multiple Threads/Cores Using the UltraSPARC T1 –D
 Dimitris Kaseridis and Lizy John, University of Texas at Austin

 

     An Early Performance Evaluation of the SiCortex SC648  

       Kevin J. Baker, Kei Davis, Darren J. Kerbyson, Mike Lang, Scott Pakin and Jose Carlos Sancho; Los Alamos National Laboratory

   

   3:00 - 3:30     Break

 

   3:30 - 5:00     Session 3:

                           

     Distributed Test Vector Storage for Safety-Critical NoC-based Systems
 Jason Lee and Rabi Mahopatra, Texas A&M University

 

     Fuce: A Continuation –based Non-Interruptible Multithreading Processor

Satoshi Amamiya, Ryuzo Hasegawa, Hiroshi Fujita and Makoto Amamiya, Kyushu University

 

     A Micro-Architectural Power-Saving Technique for D-NUCA Caches
Alessandro Bardine, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete and, Universita di Pisa, Italy and Per Stenstrom, Chalmers University of Technology, Sweden

 

 


 

Keynote: Dynamic Synthesis for Processor Overlays

                  Doug Burger, Department of Computer Science, University of Texas at Austin

 

            Abstract:

Future processors must exploit parallelism without undue programmer complexity, be power efficient, tolerate process variance, and be amenable to heavy distribution on chip.  In this talk, I will introduce a new extension of our recent Composable Processors work,  called Processor Overlays.  The central idea is to create virtual processors out of a technique termed Dynamic Synthesis, which aggregates distributed microarchitectural structures together to form highly configurable processors that are a good topologic match to the software workloads. While this particular implementation relies on an EDGE instruction set, it will work with any implementation that provides an low rate of control points, such as register renaming and branch predictions.
 

Bio:

Doug Burger is an Associate Professor at the University of Texas at Austin.  Starting in May, he will direct the new Computer Architecture group at Microsoft Research.  He received his B.S. in Computer Science from Yale University and his M.S. and Ph.D. from the University of Wisconsin-Madison.  His research interests include computer architecture,  supercomputing, compiler design and implementation, as well as the implications of novel computing technologies.  He co-led the TRIPS project at UT-Austin, which recently completed building a full system prototype of a scalable, tile-based out-of-order processor design.  He received the ACM Maurice Wilkes Award in 2006 for his work in novel, technology scalable microarchitures, including EDGE instruction sets and Non-Uniform Cache Architectures (NUCA caches). He is a Senior Member of ACM and IEEE, and is Chair of ACM SIGARCH.