Summary: The rapid scaling of machine learning (ML) workloads, particularly large language models, has intensified the need for system-level performance modeling techniques that can reason about training behavior across multiple accelerator architectures, system scales, and modeling fidelities. However, today’s ML performance studies are fragmented: simulators are typically architecture-specific, training models are tied to specialized workload representations which can require large compute systems to collect traces. This fragmentation makes it difficult for researchers and system designers to compare results, reuse workflows, or reason consistently across platforms and tools. This tutorial highlights the opportunities and challenges in reasoning about performance trends, fidelity trade-offs, and modeling assumptions illustrated through concrete examples. The tutorial emphasizes methodology, modeling choices, and interpretation, rather than championing a new simulator. Furthermore, the tutorial aims at introducing the participant a collective API extension to ASTRA-sim’s system layer, which would allow modelling arbitrary collective.

Summary: As the computational demands of recent AI models have grown exponentially, the importance of Neural Processing Units (NPUs) has increased. This trend has created a strong need for frameworks that can both broadly support the compilation of state-of-the-art DNN models for inference and training via AI compilers and provide fast and accurate NPU simulation across diverse scenarios, thereby facilitating NPU architecture research and development. In this tutorial, we introduce PyTorchSim, a framework designed to meet these demands by leveraging PyTorch’s compilation capabilities (i.e., torch.compile). We first guide participants through an end-to-end workflow, covering basic environment setup, model mapping, and performance log analysis. Building on this foundation, we systematically explore PyTorchSim’s internal design, execution flow, and integrated compiler–simulator stack. Finally, we provide a hands-on session on implementing custom units and instructions to extend NPU models. Through these exercises, participants gain a practical understanding of how to modify key components of PyTorchSim, including its MLIR-based compiler backend, Gem5, and Spike, to support new architectural features.