The 6th International Workshop on Unique Chips and Systems (UCAS-6)


To be held in conjunction with
the 43rd Annual IEEE/ACM International Symposium on Microarchitecture (

December 4, 2010

Atlanta, GA, USA






  8:50am -   9:00am   Welcome

  9:00am - 10:00am   Keynote: Prof. Sudhakar Yalmanchili, Georgia Institute of Technology

                               "Software Challenges for Heterogeneous Architectures"


10:00am - 10:30am   Coffee Break

10:30am - 12:00pm  Session I: Computer Architecture - 1  (Session Chair: Dhireesha Kudithipudi, RIT)


Early Experience with Profiling and Optimizing Distributed Shared Cache Performance on Tilera’s Tile Processor

  Inseok Choi, University of Maryland at College Park

  Minshu Zhao, University of Maryland at College Park

  Xu Yang, University of Maryland at College Park

  Donald Yeung, University of Maryland at College Park


A Formalized Task Migration Framework for Multiple Configurable Processors Shared Memory SoC Platforms

  Hao Shen, TIMA Laboratory, France

  Frédéric Pétrot, TIMA Laboratory, France


Forest Fires: improving a Cache Replacement Algorithm (Work-in-progress)

  Filipe Montefusco Scoton, University of Sao Paulo

  Mario Donato Marino, University of Virginia

  Jorge Mamoru Kobayashi, University of Sao Paulo


Integral Parallel Architecture in System-on-Chip Designs (Work-in-progress)

  Gheorghe M. Ştefan, Politehnica University of Bucharest, Romania


12:00pm -   1:30pm  Lunch

  1:30pm -   3:00pm  Session II: Computer Architecture - 2   (Session Chair: Chen Liu, FIU)


Confusion by All Means

  Muhammad Faisal Iqbal, University of Texas at Austin

  Lizy K. John, University of Texas at Austin


Validation of Synthetic Benchmarks by Measurement (Invited)

  Jungho Jo, University of Texas at Austin

  Lizy K. John, University of Texas at Austin

  Michele Reese, Freescale Semiconductor

  Jim Holt, Freescale Semiconductor


Selection of Representative Simulation Point using Performance Metric-based Similarity (Work-in-progress)

  Satish Raghunath, University of Texas at San Antonio

  Byeong Kil Lee, University of Texas at San Antonio


Marching Memory: designing computers to avoid the Memory Bottleneck (Work-in-progress)

  Tadao Nakamura, Keio University, Japan

  Michael J. Flynn, Stanford University


  3:00pm -   3:30pm  Coffee Break

  3:30pm -   5:00pm  Session III: VLSI Design   (Session Chair: Byeong Kil Lee, UTSA)


Lightweight Energy Prediction Filters for Solar-Powered Wireless Sensor Networks

  Cory E. Merkel, Rochester Institute of Technology

  Dhireesha Kudithipudi, Rochester Institute of Technology

  Andres Kwasinski, Rochester Institute of Technology


An Ultra Low Power Digitally Controlled Oscillator with Low Jitter and High Resolution

  Nasser Erfani Majd, Tarbiat Modares University (TMU), Iran

  Mojtaba Lotfizad, Tarbiat Modares University (TMU), Iran

  Arash Abadian, Tarbiat Modares University (TMU), Iran

  Mohammad Bagher Ghaznavi Ghoushchi, Shahed University, Iran


Early Stage Trade-offs Analysis in Reconfigurable H.264 Video Design (Work-in-progress)

  Youngsoo Kim, North Carolina State University

  Kyungsu Kim, Electronics and Telecommunications Research Institute (ETRI), Korea

  Seongmo Park, Electronics and Telecommunications Research Institute (ETRI), Korea


RSA Cryptography Acceleration for Embedded System (Work-in-progress)

  Rolando Duarte, Florida International University

  Chen Liu, Florida International University

  Xinwei Niu, Florida International University







  • Title: Software Challenges for Heterogeneous Architectures


  • Biography: Dr. Sudhakar Yalamanchili earned his Ph.D degree in Electrical and Computer Engineering 1984 from the University of Texas at Austin. Upon graduation, he joined Honeywell’s Systems and Research Center in Minneapolis working on embedded multiprocessor architectures.  He joined the ECE faculty at Georgia Tech in 1989 where he is now a Joseph M. Pettit Professor of Computer Engineering. He is the author of VHDL Starters Guide, 2nd edition, Prentice Hall 2004, VHDL: From Simulation to Synthesis, Prentice Hall, 2000, and co-author with J. Duato and L. Ni, of Interconnection Networks: An Engineering Approach, Morgan Kaufman, 2003. His current research interests lie in addressing the software challenges of heterogeneous architectures, integration of interconnection network and memory systems’, and solutions to power and thermal issues in many core architectures. Since 2003 he has been a Co-Director of the NSF Industry University Cooperative Research Center on Experimental Computer Systems at Georgia Tech.

    Dr. Yalamanchili contributes professionally with regular service on editorial boards and conference program committees. Most recently he is a General Co-Chair of the 2010 IEEE/ACM International Symposium on Microarchitecture (MICRO).