2 TUTORIALS (March 28, 2010)
RAMP Simulator Tutorial: Protoflex, FAST, HAsim, and RAMP-Gold (full-day)
Organizer: Derek Chiou, University of Texas at Austin
Abstract: Accurate architectural simulators are a key tool used in architectural research to verify architectural intuition. However, architectural simulators are generally very slow, running at four or more orders of magnitude slower than a single core machine and even slower when simulating a multicore machine. The RAMP collaborative is a group of academics and industry researchers who are developing methods to use field programmable gate arrays (FPGAs) to accelerate and/or implement multicore architectural simulators. In thus tutorial, we will describe, demonstrate, and provide hands-on experiences on the following four full-system RAMP simulators: CMU's Protoflex (Sparc V9), UT Austin's FAST (x86), Intel/MIT's HAsim (Alpha), and Berkeley's RAMP-Gold (Sparc V8).
10:30 Protoflex continued
Tutorial: Intel Core i7 and Intel Xeon 5500 Microarchitecture, Optimization and Performance Analysis (full-day)
Presenter: David Levinthal, Intel
Abstract: A series of lectures covering Intel’s new microprocessor family and performance analysis and SW optimization for the new processors. An in depth discussion into the Intel Xeon 5500 microarchitecture lays the ground work. This is followed by some early learnings by the Intel compiler team on optimizations for the new microarchitecture. This is followed by an extended discussion of PMU (performance monitoring unit) based performance analysis and its incorporation into features of the Intel® PTU eclipse based performance analysis tool. This is then followed by a discussion of NUMA optimization issues and their identification. Finally a demonstration of the PTU tool on precollected Intel Xeon 5500 performance data to tie all of this together.
8:15 Intel(r) Corei7 microarchitecture overview [PDF]
10:30 Compiler development learnings [PDF]
11:00 Performance Analysis on Intel(r) Corei7 Part I [PDF]
13:30 Performance Analysis on Intel(r) Corei7 Part II [PDF]
15:00 NUMA Analysis on Intel(r) Corei7 [PDF]
15:30 Pulling it all together: Intel(r) Performance Tuning Utility usage demonstration on real code [PDF]
VPACT workshop has been cancelled
Dr. David Levinthal's Bio: Principal responsibilities: Performance analysis and SW optimization. This focuses on event based sampling silicon capabilities (specification and validation), performance tools specification and validation and last level processor enabling support. Levinthal has been involved in these activities for close to ten years. Prior to this he was the lead support engineer for the Intel® Itanium™ Processor project, after having done SW, OS and HW support for the Intel Super Computer Systems Division. He has been employed at Intel for 16 years, including close to 2 years as a contractor. Prior to joining Intel Dr. Levinthal was a tenured Professor at Florida State University for ten years, specializing in experimental particle physics, working at Fermi National Laboratory and CERN. He has a Ph.D. and two masters degrees from Columbia University and a B.A. from University of California at Berkeley. His academic honors include a Sloan Fellowship, an NSF PYI award and the DOE OJI award. He owned and ran a small winery in Oregon for ten years, while employed at Intel. He first learned basic and fortran in the early 1960’s from his father.