To be held in conjunction with IEEE International Symposium on Performance  Analysis of Systems and Software (ISPASS2009)

April 26, 2009

Boston, Massachusetts, USA



8:00 -     9:00     Breakfast

9:00 -     9:45     Registration

9:45 -   10:00     Welcome


10:00 - 11:00    Keynote: The New Paradigm of the High Performance and Low Power Full Custom Design Method Based on Nanotechnology

                             Yong-Bin Kim, Department of Electrical and Computer Engineering at Northeastern University


11:00 -  12:00     Session 1:


     NoCBench: A Benchmarking Platform for Network on Chip [PDF]
Suman K. Mandal, Texas A&M University

        Nikhil Gupta, Texas A&M University

        Ayan Mandal, Texas A&M University

        Javier Malave, Texas A&M University

       Jason D. Lee, Texas A&M University

       Rabi N. Mahapatra, Texas A&M University


     A Study of a Continuation-based Fine-grain Multithreaded Operating System CEFOS [PDF]
  Shigeru Kusakabe, Kyushu University

        Hideo Taniguchi, Okayama University

        Makoto Amamiya, Osaka Institute of Technology



12:00 - 1:30     Lunch


1:30 - 3:00     Session 2:                           


     ThresHot: An Aggressive Task Scheduling Approach in CMP Thermal Design [PDF] [slide]
  Lin Li, University of Pittsburgh

        Xiuyi Zhou, University of Pittsburgh

        Jun Yang, University of Pittsburgh

       Victor Puchkarev, University of Pittsburgh


     Subthreshold Design Space Exploration for Gaussian Normal Basis Multiplier [PDF]
H. Kanitkar, Rochester Institute of Technology

        D. Kudithipudi, Rochester Institute of Technology


     Cache Capacity and Memory Bandwidth Optimization of Highly Threaded Processors [PDF]

        Jeff Stuecheli, IBM

              Lizy Kurian John, The University of Texas at Austin


   3:00 - 3:30     Break


   3:30 - 5:00     Session 3:


     Investigating design tradeoffs in S-NUCA based CMP systems [PDF]
  P. Foglia, University of Pisa

        C.A. Prete, University of Pisa

        M. Solinas, University of Pisa

        F. Panicucci, IMT Lucca


     Optimizing a Multi-Core Processor for Message-Passing Workloads [PDF]

  Niladrish Chatterjee, University of Utah

  Seth H. Pugsley, University of Utah

  Josef Spjut, University of Utah

  Rajeev Balasubramonian, University of Utah


     Parallel Assertion Processing using Memory Snapshots [PDF]
 Junaid Haroon Siddiqui, The University of Texas at Austin

       Muhammad Faisal Iqbal, The University of Texas at Austin

       Derek Chiou, University of Texas at Austin




Keynote: The New Paradigm of the High Performance and Low Power Full Custom Design Method Based on Nanotechnology

                   Yong-Bin Kim, Department of Electrical and Computer Engineering at Northeastern University



Over the past few decades there has been an increased focus on scaling down the size of transistors in CMOS circuits to improve the speed of  devices, density of devices on a given chip. As the physical gate length is reduced to below 65 nm, many device-level effects such as large parametric variations and exponential increase in leakage current have substantially affected the I-V characteristics of traditional MOSFETs, thus resulting in major concerns for scaling down the feature size of these devices. A possible approach to meet the challenges of nano scale CMOS consists of utilizing new circuit techniques together with alternative technologies to replace conventional MOSFET-based technology. This presentation will go over the challenging issues of the current nanoscale integrated circuit design issues and present possible solutions based on emerging nanoscale device technology.




Professor Yong-Bin Kim received the B.S. degree in Electrical Engineering from Sogang University in Seoul, South Korea, the M.S. degree and PH.D both in Computer Engineering from New Jersey Institute of Technology and Colorado State University, respectively. Prof. Kim was with Electronics and Telecommunications Research Institute in South Korea as a Member of technical Staff. He was with Intel Corp. as a Senior Design Engineer involving in micro-controller chip design and Intel P6 microprocessor chip design, and also he was with Hewlett Packard Co.,Fort Collins, Colorado as a Member of Technical Staff involving in HP PA-8000 RISC microprocessor chip design. He was with Sun Microsystems, Palo Alto, California as an individual contributor, and involved in 1.5GHz Ultra Sparc5 CPU chip design before he moved to the Dept. of Electrical Engineering of the University of Utah as a faculty member. He is currently an associate professor in the Department of Electrical and Computer Engineering at Northeastern University. His research focuses on low power analog and digital circuit design, high speed low power VLSI circuit design and methodology, and novel circuit design based on nanoelectronics.