Day 1

April 10



-Tutorial #1: Energy Efficient Data Centers and Systems (full-day: 8:30AM -  )     [Lunch on your own]
IBM Research, Austin


-Tutorial #2: MV5: A Reconfigurable Simulator for Heterogeneous Multicore Architectures (half-day: 1:30PM - )    [Lunch on your own]
Jiayuan Meng, Argonne National Lab


Day 2

April 11



  8:45 -  9:00  Welcome by General and Program Chairs

  9:00 -10:00  Keynote I  The Era of Heterogeneity: Are we prepared?

10:30 -12:10  Session 1

12:10 -  1:30  Lunch

  1:30 -  3:10  Session 2

  3:30 -  4:45  Session 3

  5:00 -  6:30  Reception  &

                      Poster Session

Day 3

April 12


  9:00 - 10:00  Keynote II  Integrated Modeling Challenges in Extreme-Scale Computing

10:30 -12:10  Session 4 

12:10 -  1:30  Lunch

  1:30 -  3:35  Session 5

  3:50 -  5:30  Session 6

  5:30 -          Concluding Remarks, Best Paper Award



Day 1 - April 10 (Sunday)


Day 2 - April 11 (Monday)


    8:45 -   9:00      Welcome (by the general and program chairs)

    9:00 - 10:00     Keynote I     The Era of Heterogeneity: Are we prepared?  Ravi Iyer (Intel)

                               (Session Chair: Rajeev Balasubramonian, Univ. of Utah)




10:30 - 12:10     Session 1: Best Paper Nominees                      

                             (Session Chair: David Christie, AMD)


12:10 - 1:30     Lunch


  1:30 - 3:10     Session 2: Memory Hierarchies   

                           (Session Chair: Suzanne Rivoire, Sonoma State Univ.)


  3:30 - 4:45     Session 3: Tracing

                           (Session Chair: Tom Wenisch, Univ. of Michigan)


 5:00 - 6:30     Reception and Poster Session




Day 3 - April 12 (Tuesday)


    9:00 -  10:00     Keynote II    Integrated Modeling Challenges in Extreme-Scale Computing, Pradip Bose (IBM)   [Slides]

                                (Session Chair: David Brooks, Harvard Univ.)


  10:30 - 12:10  Session 4: Emerging Workloads

                            (Session Chair: Derek Chiou, UT Austin)

12:10 - 1:30     Lunch 


 1:30 - 3:35     Session 5: Simulation and Modeling

                          (Session Chair: David Murrell, Freescale)


   3:50 -  5:30    Session 6: Power and Reliability     

                            (Session Chair: Bronis de Supinski, LLNL)


    5:30 -              Concluding Remarks, Best Paper Award



Keynote I:  The Era of Heterogeneity: Are we prepared?

Bio: Ravi Iyer is a Principal Engineer and Director of SoC Platform Architecture research group in Intel Labs. His research focus is on future SoC and CMP architectures, with specific emphasis on small cores, accelerators, cache/memory hierarchies, fabrics, QoS, emerging applications and performance evaluation. He has published 120+ papers and has filed 30+ patent applications. He will serve as the General Co-Chair for ISCA 2011 and was the Program Co-Chair for ANCS 2010. He is also an Associate Editor for ACM TACO and was previously an Associate Editor for IEEE TPDS. He has served on program committees for many conferences and workshops. Ravi received his Ph.D. in Computer Science from Texas A\&M University.

Abstract: Usage models and applications are rapidly changing as a new class of devices (smart phones, smart TVs, etc) and rich cloud computing services (on datacenter servers) enter the marketplace. In this talk, I will start by describing some key examples of these radical changes in usage models, applications and devices. I will then highlight why the next decade of computing (clients and servers) will be based on heterogeneous architectures consisting of asymmetric cores, accelerators and hybrid cache/memory structures. The rest of the talk will be an in-depth discussion of the power/performance analysis challenges for heterogeneous architectures, such as (i) how do we analyze applications to determine the right mix of cores and accelerators, (ii) how do we provide performance/power prediction techniques for efficient OS scheduling on heterogeneous architectures?, (iii) how do we enable runtimes and applications to achieve the required QoS on heterogeneous architectures?, (iv) how do simulation/emulation methodologies and infrastructure have to change for rapid and consistent heterogeneous architecture exploration? For each of these, I will also give examples of work that is on-going and outline potential areas for future work on performance/power analysis for heterogeneous architectures.


Keynote II: Integrated Modeling Challenges in Extreme-Scale Computing


Bio: Pradip Bose is a Research Staff Member and Manager of the Reliability- and Power-Aware Microarchitectures Department at IBM T. J. Watson Research Center. He has been with IBM for over twenty-five years, and has been involved in the definition and pre-silicon modeling of virtually all IBM POWER-series microprocessors. Dr. Bose is a member of the IBM Academy of Technology and is an IBM Master Inventor. He is a Fellow of IEEE.


Abstract: Extreme-scale computer systems of the future target orders of magnitude improvement in performance over current large-scale server or supercomputing systems. These targets must be achieved for the same power consumption and reliability at the system level. Accomplishing the goal requires investment in new generation integrated pre-silicon modeling environments that allow rapid exploration of power, performance and reliability tradeoffs. In this talk, I present an overview of the alluded modeling challenges and methods of hierarchical abstractions to ease the pre-silicon simulation bottleneck.